元器件交易网www.cecb2b.comSN54LV1A, SN74LV1A8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERSSCLS403H − APRIL 1998 − REVISED APRIL 2005D2-V to 5.5-V VCC OperationDMax tpd of 10.5 ns at 5 VDTypical VOLP (Output Ground Bounce)DDDLatch-Up Performance Exceeds 250 mA PerDJESD 17ESD Protection Exceeds JESD 22− 2000-V Human-Body Model (A114-A)− 200-V Machine Model (A115-A)− 1000-V Charged-Device Model (C101)<0.8 V at VCC = 3.3 V, TA = 25°CTypical VOHV (Output VOH Undershoot)>2.3 V at VCC = 3.3 V, TA = 25°CSupport Mixed-Mode Voltage Operation onAll PortsSN54LV1A...J OR W PACKAGESN74LV1A...D, DB, DGV, NS,OR PW PACKAGE(TOP VIEW)SN74LV1A...RGY PACKAGE(TOP VIEW)SN54LV1A...FK PACKAGE(TOP VIEW)GNDNC − No internal connectiondescription/ordering informationThe ’LV1A devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V VCC operation.ORDERING INFORMATIONTAPACKAGE†QFN − RGYSOIC − DSOP − NS−40°C to 85°CSSOP − DBTSSOP − PWTVSOP − DGVCDIP − J−55°C to 125°CCFP − WLCCC − FKReel of 1000Tube of 50Reel of 2500Reel of 2000Reel of 2000Tube of 90Reel of 2000Reel of 250Reel of 2000Tube of 25Tube of 150Tube of 55ORDERABLEPART NUMBERSN74LV1ARGYRSN74LV1ADSN74LV1ADRSN74LV1ANSRSN74LV1ADBRSN74LV1APWSN74LV1APWRSN74LV1APWTSN74LV1ADGVRSNJ54LV1AJSNJ54LV1AWSNJ54LV1AFKLV1ASNJ54LV1AJSNJ54LV1AWSNJ54LV1AFKLV1ATOP-SIDEMARKINGLV1ALV1A74LV1ALV1A†Package drawings, standard packing quantities, thermal data, symbolization, and PCB designguidelines are available at www.ti.com/sc/package.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.UNLESS OTHERWISE NOTED this document contains PRODUCTIONDATA information current as of publication date. Products conform tospecifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of allparameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265Copyright 2005, Texas Instruments Incorporated•QDGNDNCCLKCLRABQAQBQCQDGND1234567141312111098VCCQHQGQFQECLRCLK11413QH12QG11QF10QE9CLRBANCVCCQHQANCQBNCQC4567832120191817161514910111213VCCABQAQBQCQD2345678QGNCQFNCQECLK1元器件交易网www.cecb2b.comSN54LV1A, SN74LV1A8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERSdescription/ordering information (continued)These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gatedserial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new dataand resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input,which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clockis high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-leveltransition of the clock (CLK) input.FUNCTION TABLEINPUTSCLRLHHHHCLKXL↑↑↑AXXHLXBXXHXLQALQA0HLLOUTPUTSQB...QHLQB0QAnQAnQAnLQH0QGnQGnQGnSCLS403H − APRIL 1998 − REVISED APRIL 2005QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,before the indicated steady-state input conditions wereestablished.QAn, QGn = the level of QA or QG before the most recent↑ transition of the clock: indicates a 1-bit shift.logic diagram (positive logic)CLK8AB12R9C11DC11DRC11DRC11DRC11DRC11DRC11DRC11DRCLR3QA4QB5QC6QD10QE11QF12QG13QHPin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comSN54LV1A, SN74LV1A8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERSSCLS403H − APRIL 1998 − REVISED APRIL 2005typical clear, shift, and clear sequencesCLRSerial InputsABCLKQAQBQCOutputsQDQEQFQGQHClearClearPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSN54LV1A, SN74LV1A8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERSabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 VInput voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 VVoltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 VOutput voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 VInput clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mAOutput clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mAContinuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAPackage thermal impedance, θJA(see Note 3):D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W(see Note 3):DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W(see Note 3):DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W(see Note 3):NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W(see Note 3):PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W(see Note 4):RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/WStorage temperature range, Tstg −65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.2.This value is limited to 5.5 V maximum.3.The package thermal impedance is calculated in accordance with JESD 51-7.4.The package thermal impedance is calculated in accordance with JESD 51-5.SCLS403H − APRIL 1998 − REVISED APRIL 20054POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comSN54LV1A, SN74LV1A8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERSSCLS403H − APRIL 1998 − REVISED APRIL 2005recommended operating conditions (see Note 5)SN54LV1AMINVCCSupply voltageVCC = 2 VVCC = 2.3 V to 2.7 VVCC = 3 V to 3.6 VVCC = 4.5 V to 5.5 VVCC = 2 VVCC = 2.3 V to 2.7 VVCC = 3 V to 3.6 VVCC = 4.5 V to 5.5 V00VCC = 2 VVCC = 2.3 V to 2.7 VVCC = 3 V to 3.6 VVCC = 4.5 V to 5.5 VVCC = 2 VVCC = 2.3 V to 2.7 VVCC = 3 V to 3.6 VVCC = 4.5 V to 5.5 VVCC = 2.3 V to 2.7 VVCC = 3 V to 3.6 VVCC = 4.5 V to 5.5 V21.5VCC ×0.7VCC ×0.7VCC ×0.70.5VCC ×0.3VCC ×0.3VCC ×0.35.5VCC−50−2−6−125026122001002000MAX5.5SN74LV1AMIN21.5VCC ×0.7VCC ×0.7VCC ×0.70.5VCC ×0.3VCC ×0.3VCC ×0.35.5VCC−50−2−6−1250261220010020ns/VmAµAmAVVMAX5.5UNITVVIHHigh-level input voltageVILLow-level input voltageVIVOInput voltageOutput voltageVVµAIOHHigh-level output currentIOLLow-level output current∆t/∆vInput transition rise or fall rateTAOperating free-air temperature−55125−4085°CNOTE 5:All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTEST CONDITIONSIOH = −50 µAIOH = −2 mAIOH = −6 mAIOH = −12 mAIOL = 50 µAIOL = 2 mAIOL = 6 mAIOL = 12 mAVI = 5.5 V or GNDVI = VCC or GND,VI or VO = 0 to 5.5 VVI = VCC or GNDIO = 0VCC2 V to 5.5 V2.3 V3 V4.5 V2 V to 5.5 V2.3 V3 V4.5 V0 to 5.5 V5.5 V03.3 V2.2SN54LV1AMINVCC−0.122.483.80.10.40.440.55±12052.2TYPMAXSN74LV1AMINVCC−0.122.483.80.10.40.440.55±1205µAµAµApFVTYPMAXUNITVOHVVOLIIICCIoffCiPRODUCT PREVIEW information concerns products in the formative ordesign phase of development. Characteristic data and otherspecifications are design goals. Texas Instruments reserves the right tochange or discontinue these products without notice.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.comSN54LV1A, SN74LV1A8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERStiming requirements over recommended operating free-air temperature range, VCC = 2.5 V±0.2 V(unless otherwise noted) (see Figure 1)TA = 25°CMINMAXtwtsuthPulse durationSetup timeHold timeCLR lowCLK high or lowData before CLK↑CLR inactiveData after CLK↑66.56.53−0.5SN54LV1AMIN6.57.58.530MAXSN74LV1AMIN6.57.58.530MAXUNITnsnsnsSCLS403H − APRIL 1998 − REVISED APRIL 2005timing requirements over recommended operating free-air temperature range, VCC = 3.3 V±0.3 V(unless otherwise noted) (see Figure 1)TA = 25°CMINMAXtwtsuthPulse durationSetup timeHold timeCLR lowCLK high or lowData before CLK↑CLR inactiveData after CLK↑5552.50SN54LV1AMIN5562.50MAXSN74LV1AMIN5562.50MAXUNITnsnsnstiming requirements over recommended operating free-air temperature range, VCC = 5 V±0.5 V(unless otherwise noted) (see Figure 1)TA = 25°CMINMAXtwtsuthPulse durationSetup timeHold timeCLR lowCLK high or lowData before CLK↑CLR inactiveData after CLK↑554.52.51SN54LV1AMIN554.52.51MAXSN74LV1AMIN554.52.51MAXUNITnsnsnsswitching characteristics over recommended operating free-air temperature range,VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)PARAMETERfmaxtpdtPHLtpdtPHLCLKCLRCLKCLRQQQQFROM(INPUT)TO(OUTPUT)LOADCAPACITANCECL = 15 pFCL = 50 pFCL = 15 pFTA = 25°CMINTYPMAX55*45105*859.2*8.6*11.510.817.6*16*21.119.5SN54LV1AMIN50*401*1*1120*18*2422MAXSN74LV1AMIN5040111120182422MAXUNITMHznsCL = 50 pFns* On products compliant to MIL-PRF-38535, this parameter is not production tested.PRODUCT PREVIEW information concerns products in the formative ordesign phase of development. Characteristic data and otherspecifications are design goals. Texas Instruments reserves the right tochange or discontinue these products without notice.6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.comSN54LV1A, SN74LV1A8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERSSCLS403H − APRIL 1998 − REVISED APRIL 2005switching characteristics over recommended operating free-air temperature range,VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)PARAMETERfmaxtpdtPHLtpdCLKCLRCLKQFROM(INPUT)TO(OUTPUT)LOADCAPACITANCECL = 15 pFCL = 50 pFCL = 15 pFCL = 50 pFTA = 25°CMINTYPMAX80*50155*1206.4*6*8.312.8*12.8*16.316.3SN54LV1AMIN65*451*1*1115*15*18.518.5MAXSN74LV1AMIN65451111151518.518.5MAXUNITMHznsnstPHLCLR7.9* On products compliant to MIL-PRF-38535, this parameter is not production tested.Qswitching characteristics over recommended operating free-air temperature range,VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)PARAMETERfmaxtpdtPHLtpdCLKCLRCLKQFROM(INPUT)TO(OUTPUT)LOADCAPACITANCECL = 15 pFCL = 50 pFCL = 15 pFCL = 50 pFTA = 25°CMINTYPMAX125*85220*1654.5*4.2*69*8.6*1110.6SN54LV1AMIN105*751*1*1110.5*10*12.512.5MAXSN74LV1AMIN10575111110.51012.512.5MAXUNITMHznsnstPHLCLR5.8* On products compliant to MIL-PRF-38535, this parameter is not production tested.Qnoise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)PARAMETERVOL(P)VOL(V)VOH(V)VIH(D)Quiet output, maximum dynamic VOLQuiet output, minimum dynamic VOLQuiet output, minimum dynamic VOHHigh-level dynamic input voltage2.310.99SN74LV1AMINTYP0.28−0.223.09MAX0.8−0.8UNITVVVVVVIL(D)Low-level dynamic input voltageNOTE 6:Characteristics are for surface-mount packages only.operating characteristics, TA = 25°CPARAMETERCpdPower dissipation capacitanceTEST CONDITIONSCL = 50 pF,f = 10 MHzVCC3.3 V5 VTYP48.147.5UNITpFPRODUCT PREVIEW information concerns products in the formative ordesign phase of development. Characteristic data and otherspecifications are design goals. Texas Instruments reserves the right tochange or discontinue these products without notice.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•7元器件交易网www.cecb2b.comSN54LV1A, SN74LV1A8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERSPARAMETER MEASUREMENT INFORMATIONRL = 1 kΩS1VCCOpenGNDSCLS403H − APRIL 1998 − REVISED APRIL 2005From OutputUnder TestCL(see Note A)TestPointFrom OutputUnder TestCL(see Note A)TESTtPLH/tPHLtPLZ/tPZLtPHZ/tPZHOpen DrainS1OpenVCCGNDVCCLOAD CIRCUIT FORTOTEM-POLE OUTPUTSLOAD CIRCUIT FOR3-STATE AND OPEN-DRAIN OUTPUTSVCC0 VVCCtsuData Input0 V50% VCCthVCC50% VCC0 VVOLTAGE WAVEFORMSSETUP AND HOLD TIMESVCCOutputControltPZLOutputWaveform 1S1 at VCC(see Note B)tPZHOutputWaveform 2S1 at GND(see Note B)50% VCC50% VCCVCC50% VCC50% VCCtPLZ≈VCCVOL + 0.3 VVOLtPHZVOH − 0.3 VVOH≈0 V0 VTiming Inputtw50% VCCInput50% VCCVOLTAGE WAVEFORMSPULSE DURATION50% VCCInputtPLHIn-PhaseOutputtPHLOut-of-PhaseOutput50% VCC50% VCCtPHL0 V50% VCCVOH50% VCCVOLtPLH50% VCCVOH50% VCCVOLVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESLOW- AND HIGH-LEVEL ENABLINGNOTES:A.CL includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics:PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.D.The outputs are measured one at a time, with one input transition per measurement.E.tPLZ and tPHZ are the same as tdis.F.tPZL and tPZH are the same as ten.G.tPHL and tPLH are the same as tpd.H.All parameters and waveforms are not applicable to all devices.Figure 1. Load Circuit and Voltage Waveforms8POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
PACKAGEOPTIONADDENDUM
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PACKAGINGINFORMATION
OrderableDeviceSN74LV1ADSN74LV1ADBRSN74LV1ADBRE4SN74LV1ADE4SN74LV1ADGVRSN74LV1ADGVRE4SN74LV1ADRSN74LV1ADRE4SN74LV1ANSRSN74LV1ANSRE4SN74LV1APWSN74LV1APWG4SN74LV1APWRSN74LV1APWRG4SN74LV1APWTSN74LV1APWTE4SN74LV1ARGYR
(1)
Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE
PackageTypeSOICSSOPSSOPSOICTVSOPTVSOPSOICSOICSOSOTSSOPTSSOPTSSOPTSSOPTSSOPTSSOPQFN
PackageDrawing
DDBDBDDGVDGVDDNSNSPWPWPWPWPWPWRGY
PinsPackageEcoPlan(2)
Qty1414141414141414141414141414141414
50
Green(RoHS&noSb/Br)
Lead/BallFinishCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU
MSLPeakTemp(3)Level-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-2-260C-1YEAR
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)50
Green(RoHS&noSb/Br)
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)2500Green(RoHS&
noSb/Br)2500Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)9090
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
2000Green(RoHS&
noSb/Br)2000Green(RoHS&
noSb/Br)250250
Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)
1000Green(RoHS&
noSb/Br)
Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)
EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS)orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)
Addendum-Page1
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PACKAGEOPTIONADDENDUM
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(3)
MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
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Addendum-Page2
元器件交易网www.cecb2b.comMECHANICAL DATAMPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000DGV (R-PDSO-G**) 24 PINS SHOWN0,230,1313PLASTIC SMALL-OUTLINE 0,40240,07M0,16 NOM4,504,306,606,20Gage Plane0,250°–ā8°1A120,750,50Seating Plane1,20 MAX0,150,050,08PINS **DIMA MAXA MIN143,703,50163,703,50205,104,90245,104,90387,907,704,809,605611,4011,204073251/E 08/00NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.Falls within JEDEC:24/48 Pins – MO-15314/16/20/56 Pins – MO-194POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
元器件交易网www.cecb2b.com
元器件交易网www.cecb2b.com元器件交易网www.cecb2b.comMECHANICAL DATAMSSO002E – JANUARY 1995 – REVISED DECEMBER 2001DB (R-PDSO-G**) 28 PINS SHOWN0,65280,380,22150,15MPLASTIC SMALL-OUTLINE0,250,095,605,008,207,40Gage Plane1A140°–ā8°0,250,950,55Seating Plane2,00 MAX0,05 MIN0,10PINS **DIMA MAX146,50166,50207,50248,502810,503010,503812,90A MIN5,905,906,907,909,909,9012,304040065/E 12/01NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-150POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 MECHANICAL DATA PW (R-PDSO-G**) 14 PINS SHOWNPLASTIC SMALL-OUTLINE PACKAGE0,651480,300,190,10M0,15 NOM4,504,306,606,20Gage Plane0,251A70°–8°0,750,50Seating Plane1,20 MAX0,150,050,10PINS **DIMA MAX83,10145,10165,10206,60247,902,80A MIN2,904,904,906,407,709,6040400/F 01/97NOTES:A.B.C.D.All linear dimensions are in millimeters.This drawing is subject to change without notice.Body dimensions do not include mold flash or protrusion not to exceed 0,15.Falls within JEDEC MO-153POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
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